This invention relates to a complementary MOS transistor allowing for high density integration.
FIG. 1 shows a memory cell circuit which has the smallest number of elements among the known memory cell arrangements of a static semiconductor memory dvice dispensing with a refreshing operation. The memory cell of FIG. 1 comprises a first N channel depletion type (D type) MOS transistor T.sub.1, one terminal (drain) of which is connected to one power source V.sub.DD ; a third P channel D type MOS transistor T.sub.3, one terminal (drain) of which is connected to the other power source V.sub.SS (grounding potential); a second N channel D type MOS transistor T.sub.2 connected between the other terminals (sources) of the first and third MOS transistors T.sub.1, T.sub.3 ; and a fourth MOS transistor T.sub.4 which is connected between the junction of the first and second MOS transistors T.sub.1, T.sub.2 and a bit line BL, and whose gate is connected to a word line WL to act as a transfer gate. The gates of the first MOS transistor T.sub.1 and the third MOS transistor T.sub.3 are connected to the junction of the first and second MOS transistors. The gate of the second MOS transistor T.sub.2 is connected to the second power source V.sub.SS. Two stability phases corresponding to the logic levels "0" and "1" are produced at the junction of the first and second MOS transistors T.sub.1, T.sub.2 owing to negative resistances of the MOS transistors T1 and T2.
The above-mentioned memory cell comprises N- and P-type MOS transistors referred to as "complementary MOS transistors" (abbreviated as CMOS). FIG. 2 schematically shows a cross section of a prior CMOS inverter. The gates of a P channel transistor T.sub.P and an N channel transistor T.sub.N are jointly connected to constitute an input terminal IN, and the drains of both transistors T.sub.P, T.sub.N are jointly connected to form an output terminal OUT, thus providing a CMOS inverter. This CMOS inverter is known to have the great advantages that its power consumption is small; amplification is effected at a high rate when the inverter is shifted from one output state to another; and said shifting takes a very short time.
As apparent from FIG. 2, however, a P channel transistor T.sub.P and an N channel transistor T.sub.N are formed on the same substrate (shown to have an N conductivity type), making it necessary to provide an isolation region between both transistors T.sub.P, T.sub.N (between the drains of said transistor T.sub.P, T.sub.N as indicated). Therefore, integration of the prior art CMOS involves more complicated processing steps than that of the customary single channel MOS transistor, thus obstructing the elevation of integration density.
It is accordingly the object of this invention to provide CMOS transistors, wherein part of that portion of a semiconductor region in which a P channel MOS transistor is formed and part of that portion of a semiconductor region in which an N channel MOS transistor is formed constitute a common section of both MOS transistors, thereby making it unnnecessary to provide an isolation region therebetween.